| ISBN: ISBN
|
| ISBN: 0-7803-4209-7
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| ISBN: ISSN: 1089-3539
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| ISBN: DOI: 10.1109/TEST.1997.639636
|
| |
| description |
A deterministic BIST scheme is presented which requires less
hardware overhead than pseudo-random BIST but obtains better or even
complete fault coverage at the same time. It takes advantage of the
fact that any autonomous BIST scheme needs a BIST control unit for
indicating the completion of the self-test at least.
Hence, pattern counters and bit counters are always available, and
they provide information to be used for deterministic pattern
generation by some additional circuitry. This paper presents a
systematic way for synthesizing a pattern generator which needs less
area than a 32-bit LFSR for random pattern generation for all the
benchmark circuits.
|
| publisher |
International Test Conference
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| type |
Text
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| Article in Proceedings
|
| source |
In: Proc. of the 28th IEEE International Test Conference (ITC),
Washington, DC, November 1997, pp. 347-355
|
| contributor |
Rechnerarchitektur (IFI)
|
| subject |
Reliability, Testing, and Fault-Tolerance (CR B.8.1)
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| deterministic BIST
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| scan-based BIST
|